Assignments

Assignment Handling.

The class Assigns manages sets of signal assignments. Either statically in modules but also within flip-flop and multiplexer definitions.

Basic Examples

All of the following is happening within any hardware module, flip-flop or multiplexer, but can also be used within own code.

>>> import ucdp as u
>>> signals = u.Idents([
...     u.Port(u.ClkRstAnType(), "main_i"),
...     u.Port(u.UintType(8), "vec_a_i"),
...     u.Port(u.UintType(8), "vec_a_o"),
...     u.Port(u.UintType(14), "vec_b_i"),
...     u.Port(u.UintType(14), "vec_b_o"),
...     u.Port(u.UintType(14), "vec_c_o"),
...     u.Signal(u.ClkRstAnType(), "main_s"),
...     u.Signal(u.UintType(8), "vec_a_s"),
...     u.Signal(u.UintType(4), "vec_b_s"),
...     u.Signal(u.UintType(4), "vec_c_s"),
... ])
>>> assigns = u.Assigns(targets=signals, sources=signals)
>>> assigns.set_default(signals['vec_a_o'], signals['vec_a_i'])
>>> assigns.set_default(signals['vec_b_o'], signals['vec_b_i'])
>>> assigns.set(signals['vec_a_o'], signals['vec_a_s'])
>>> for assign in assigns:
...     str(assign)
'vec_a_o  <----  vec_a_s'
'vec_b_o  <----  vec_b_i'

Multiple Assignments

Multiple assignments are forbidden:

>>> assigns.set(signals['vec_a_o'], signals['vec_a_s'])
Traceback (most recent call last):
...
ValueError: 'vec_a_o' already assigned to 'vec_a_s'

Default Examples

Defaults are managed separately:

>>> for assign in assigns.defaults():
...     str(assign)
'vec_a_o  <----  vec_a_i'
'vec_b_o  <----  vec_b_i'

Mapping

With inst=True the all target signals are mapped:

>>> assigns = u.Assigns(targets=signals, sources=signals, inst=True)
>>> assigns.set_default(signals['vec_a_i'], signals['vec_a_i'])
>>> assigns.set_default(signals['vec_b_i'], signals['vec_b_i'])
>>> assigns.set(signals['vec_a_i'], signals['vec_a_s'])
>>> for assign in assigns:
...     str(assign)
'main_i  ---->  None'
'main_clk_i  ---->  None'
'main_rst_an_i  ---->  None'
'vec_a_i  ---->  vec_a_s'
'vec_a_o  <----  None'
'vec_b_i  ---->  vec_b_i'
'vec_b_o  <----  None'
'vec_c_o  <----  None'
'main_s  ---->  None'
'main_clk_s  ---->  None'
'main_rst_an_s  ---->  None'
'vec_a_s  ---->  None'
'vec_b_s  ---->  None'
'vec_c_s  ---->  None'

Assign

Bases: Object

A Single Assignment of expr to target.

Attributes:

Name	Type	Description
target	BaseSignal	Assigned identifier.
source	Source | None	Assigned expression.

name property

name

Name.

type_ property

type_

Type.

doc property

doc

Doc.

direction property

direction

Direction.

ifdef property

ifdef

IFDEF.

sign property

sign

Sign.

Assigns

Bases: Object

Assignments.

An instance of Assigns manages a set of signal assignments.

Attributes:

Name	Type	Description
targets	Idents	Identifiers allowed to be assigned.
source	Idents	Identifiers allowed to be used in assignment. targets by default.
drivers	Drivers | None	Driver tracking, to avoid multiple drivers. To be shared between multiple assignments, where only one driver is allowed.
inst	bool	All Instances Assignment Mode.
sub	bool	Sublevel Instance Assignment Mode.

is_locked property

is_locked

Locked.

lock

lock()

Lock.

set_default

set_default(target, source, cast=False, overwrite=False, filter_=None)

Set Default of target to source.

Parameters:

Name	Type	Description	Default
target	Target	Target.	required
source	Source	Source.	required
cast	bool | None	cast to target.	False
overwrite	bool	overwrite target.	False

set

set(target, source, cast=False, overwrite=False, filter_=None)

Set Assignment of target to source.

Parameters:

Name	Type	Description	Default
target	BaseSignal	Target.	required
source	Source	Source.	required
cast	bool | None	cast to target.	False
overwrite	bool	overwrite target.	False

get

get(target)

Get Assignment of target.

iter

iter(filter_=None)

Iterate over assignments.

defaults

defaults()

Iterate Over Defaults.