Clock Gate Module

glbl/clk_gate.py

from typing import ClassVar

import ucdp as u  # (1)
from fileliststandard import HdlFileList


class ClkGateMod(u.AMod):
    """Clock Gate."""

    # File Lists
    filelists: ClassVar[u.ModFileLists] = (  # (2)
        HdlFileList(),
    )

    def _build(self) -> None:
        # Port Declarations (3)
        self.add_port(u.ClkType(), "clk_i")
        self.add_port(u.ClkType(), "clk_o")
        self.add_port(u.EnaType(), "ena_i")

1. Import Data Model Library
2. A module can have any number of file lists with different names and targets.
3. Adding a port is simple as using add_port