UART Module

uart/uart.py

from typing import ClassVar

import ucdp as u  # (1)
from fileliststandard import HdlFileList
from glbl_lib.bus import BusType  # (2)
from glbl_lib.clk_gate import ClkGateMod  # (3)
from glbl_lib.regf import RegfMod  # (4)


class UartIoType(u.AStructType):
    """UART IO."""

    title: str = "UART"
    comment: str = "RX/TX"

    def _build(self) -> None:
        self._add("rx", u.BitType(), u.BWD)  # (5)
        self._add("tx", u.BitType(), u.FWD)  # (6)


class UartMod(u.AMod):
    """A Simple UART."""

    filelists: ClassVar[u.ModFileLists] = (HdlFileList(gen="full"),)

    def _build(self) -> None:
        self.add_port(u.ClkRstAnType(), "main_i")
        self.add_port(UartIoType(), "uart_i", route="create(u_core/uart_i)")
        self.add_port(BusType(), "bus_i")

        clkgate = ClkGateMod(self, "u_clk_gate")
        clkgate.con("clk_i", "main_clk_i")
        clkgate.con("clk_o", "create(clk_s)")

        regf = RegfMod(self, "u_regf")
        regf.con("main_i", "main_i")
        regf.con("bus_i", "bus_i")

        core = UartCoreMod(parent=self, name="u_core")

        core.add_port(u.ClkRstAnType(), "main_i")
        core.con("main_clk_i", "clk_s")
        core.con("main_rst_an_i", "main_rst_an_i")
        core.con("create(regf_i)", "u_regf/regf_o")

        word = regf.add_word("ctrl")
        word.add_field("ena", u.EnaType(), is_readable=True, route="u_clk_gate/ena_i")
        word.add_field("strt", u.BitType(), is_writable=True, route="create(u_core/strt_i)")


class UartCoreMod(u.ACoreMod):
    """A Simple UART."""

    filelists: ClassVar[u.ModFileLists] = (HdlFileList(gen="inplace"),)